1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a redundancy technique in a ferroelectric memory.
2. Description of the Related Art
For semiconductor memory devices, a technique (redundancy technique) for increasing the manufacturing yield is indispensable. In such a technique, redundancy spare cells are prepared in addition to primary memory cells of a necessary capacity, and defective memory cells are replaced with the spare cells for remedy.
A ferroelectric memory employs a method of arranging memory cells to be selected by a word line and spare cells to be selected by a spare word line on the same bit line so that a defective cell is replaced with a spare cell on the same bit line. In this redundancy method, if a plurality of defective cells appear on one bit line, only cells equal in number to spare word lines (spare rows) formed in advance are replaced. In addition, remedy is possible in only the same memory cell array. If defective cells concentrate in a specific memory cell array, some defective cells cannot be remedied by a corresponding redundancy cell array. However, the remaining defective cells cannot be remedied by spare cells in another memory cell array having no defective cells.
In a DRAM having a memory cell structure similar to a ferroelectric cell, an independent redundancy cell array having a smaller capacity than a main cell array is prepared outside it. Since this redundancy cell array can be replaced with unspecified memory cell arrays, the remedy efficiency increases. The bit line length in such an independent redundancy cell array having a small capacity is smaller than that in each memory cell array in the main cell array. For this reason, the bit line capacitance of the redundancy cell array is lower than that in the main cell array. In the DRAM, when the bit line capacitance decreases, the cell signal amount in a read increases. Hence, no problem arises in the sense operation in the read.
In a ferroelectric memory, however, when the bit line capacitance reaches a predetermined value, the read signal amount decreases independently of the decrease/increase in bit line capacitance in a graph having an abscissa representing the bit line capacitance and an ordinate representing the read signal amount, as shown in, e.g., FIG. 2.7.5(b) of Takashima D., et al., “A 76 mm2 8 Mb Chain Ferroelectric Memory”, 2001 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS (ISSCC 2001/SESSION2/NON-VOLATILE MEMORIES/2.7 pp. 40–41). Especially when the bit line capacitance becomes low, the decrease in signal amount is large.
For this reason, in a ferroelectric memory, if remedy is effected by using an independent redundancy cell array having a smaller capacity than the main cell array, the read signal amount decreases as the bit line capacitance decreases. As a result, operation errors may occur in a data read. Hence, the flexible redundancy technique cannot be used in a ferroelectric memory, unlike a DRAM.